Editor's Note: Multicore architectures find use across a diverse range of applications thanks to their performance and efficiency. By combining several general-purpose MCU cores — or MCU cores and ...

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To ...

The memory hierarchy (including caches and main memory) can consume as much as 50% of an embedded system power. This power is very application dependent, and tuning caches for a given application is a ...

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris ...

Open Core Protocol (OCP) [1][2] is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...

The dynamic interplay between processor speed and memory access times has rendered cache performance a critical determinant of computing efficiency. As modern systems increasingly rely on hierarchical ...

While traditional single core systems employ a dedicated cache, theintroduction of multi-core platforms presents the opportunity toconsider the shared use of cache by multiple processors. Designs ...

Some design teams creating system-on-chip (SoC) devices are fortunate to work with the latest and greatest technology nodes coupled with a largely unconstrained budget for acquiring intellectual ...

Mobile devices continue their march toward becoming powerful productivity machines. But they are also major security risks if they aren't managed properly. We look at the latest wisdom and best ...

AMD is leveraging one of its latest families of EPYC server CPUs, code-named Genoa X, in-house to run the electronic design automation (EDA) tools it uses for product development. Based on TSMC's 5-nm ...