EDN

Moving DFT to RTL overcomes test vector issues

In the IC design flow, design-for-test is often an afterthought. First, the design is coded, then simulated, then synthesized, and only after all that – usually months into the design cycle – it's ...
Electronic Design

Test Vector Compression Makes More From Less

Design automation is the key to the development of very large ICs. Optimizing the connection and layout of millions of gates to efficiently perform complex functions is not a job to which humans are ...
Semiconductor Engineering

Power-Aware Test: Addressing Power Challenges In DFT And Test

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design ...
Business Wire

DFTView and Verdi Give DFT and Test Engineers Visibility into STIL and WGL Files

EL DORADO HILLS, Calif. & HSINCHU, Taiwan--(BUSINESS WIRE)--SpringSoft, Inc., a global supplier of specialized IC design software, and Source III, Inc., a leading supplier of test vector translation ...
Semiconductor Engineering

How To Manage DFT For AI Chips

Semiconductor companies are racing to develop AI-specific chips to meet the rapidly growing compute requirements for artificial intelligence (AI) systems. AI chips from companies like Graphcore and ...
Design-Reuse

DFT software tackles test costs

BALTIMORE — The marriage of design-for-test (DFT) software with test hardware may drastically lower the cost of test, according to several companies that will present their plans at this week's ...
Design-Reuse

Moving DFT to RTL overcomes test vector issues

In the IC design flow, design-for-test is often an afterthought. First, the design is coded, then simulated, then synthesized, and only after all that - usually months into the design cycle - it's ...