EDN

Digital VLSI Design Project

Designed a 16-bit array multiplier using carry save adders and drawing layout in Cadence. Improved performance of multiplier by pipelining multiplier using flip flops and latches.
Dhaka Tribune

CVES launches course on RTL design, verification and VLSI synthesis

The American International University-Bangladesh (AIUB) inaugurated a new professional industry-focused course titled “RTL Design, Verification, Synthesis and PnR for Digital VLSI Design” on October 5 ...
Nature

FIR Filter Design and VLSI Implementation

The design of Finite Impulse Response (FIR) filters has evolved into a sophisticated discipline that balances signal-processing performance with hardware efficiency. Innovations in FIR filter design ...
Indiatimes

Summer training on VLSI design begins at IIIT-A

Prayagraj: India is a huge market for application and use of Very Large-Scale Integration (VLSI) and semiconductor ecosystem and government policy and capital is going to catalyse these two elements ...