High-performance computing (HPC) applications require IC designs with maximum performance. However, as process technology advances, achieving high performance has become increasingly challenging.

The importance of timing requirements and jitter budgets for FPGAs, ASICs, and SoCs. How to utilize the information portrayed in a clock tree to choose the most well-suited clock generator for your ...

This two-part Signal Chain Basics post is brought to you by Dean Banerjee, an applications engineer for TI's Signal and Data Path Solutions Business Unit. Part one can be found here. A good way to ...

As SoC designs continue to evolve, the complexity of reset architectures has grown significantly. Traditionally, clock tree synthesis has been a major focus due to timing challenges, but now reset ...