EDN

How to raise the RTL abstraction level and design conciseness with SystemVerilog – Part 2

As discussed in Part 1, this article proposes four steps to raise the abstraction level of current Verilog HDL designs and provide a phase wise approach to migrate to SystemVerilog. In Part 1 we ...
Design-Reuse

Staged Scenario Generation For SoC Verification

SoC (System-on-Chip) involves number of IP blocks and verification of these blocks and interaction within these blocks is a complex procedure. Various methodologies such as eRM (Cadence/Specman) [1], ...
EDN

Is IP reuse, rather that an ESL, the next level of abstraction for SoC design?

The opening-night Design Automation Conference reception last night featured a panel discussion that faced-off senior design managers against senior marketing folks from the technology infrastructure.
Design-Reuse

Transaction-Level Modelling and Debug of SoCs

System-on-Chip (SoC) designs are becoming increasingly complex. Modelling, verification, and debug facilities at RTL have become quite inadequate in the face of rising design challenges.
VentureBeat

Abstraction in programming: Taming the ones and zeros

Join our daily and weekly newsletters for the latest updates and exclusive content on industry-leading AI coverage. Learn More We can now accomplish some pretty incredible things with technology. What ...