As discussed in Part 1, this article proposes four steps to raise the abstraction level of current Verilog HDL designs and provide a phase wise approach to migrate to SystemVerilog. In Part 1 we ...

SoC (System-on-Chip) involves number of IP blocks and verification of these blocks and interaction within these blocks is a complex procedure. Various methodologies such as eRM (Cadence/Specman) [1], ...

The opening-night Design Automation Conference reception last night featured a panel discussion that faced-off senior design managers against senior marketing folks from the technology infrastructure.

System-on-Chip (SoC) designs are becoming increasingly complex. Modelling, verification, and debug facilities at RTL have become quite inadequate in the face of rising design challenges.