Munich, Germany – June 2 nd, 2020 – Codasip GmbH, the leading supplier of configurable RISC-V ® embedded processor IP, announced today that the Codasip SweRV Support Package has been extended to ...
Munich, Germany – April 23 rd, 2020 – Codasip GmbH, the leading supplier of configurable RISC-V ® embedded processor IP, announced today the official release of its new product, the Codasip SweRV Core ...
In mid-May, CHIPS Alliance announced the open sourcing of the SweRV Core EH2 and SweRV Core EL2 designed by Western Digital. These cores, as well as the earlier EH1, are now supported by Codasip’s ...
Western Digital has announced that it's completed work on its Swerv RISC-V CPU core and has published the register-transfer level (RTL) abstraction of the design. Publishing the RTL code allows other ...
Western Digital has added two new processor cores, the SweRV Core EH2 and the SweRV Core EL2, into its SweRV portfolio of microcontroller CPUs. The current processor core, the SweRV Core EH1, is based ...
Western Digital announced at the RISC-V Summit three new open-source innovations designed to support Western Digital's internal RISC-V development efforts and those of the growing RISC-V ecosystem. In ...
Western Digital has announced that it's completed work on its Swerv RISC-V CPU core and has published the register-transfer level (RTL) abstraction of the design. Publishing the RTL code allows other ...
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